The present invention pertains to multiple central processing unit (CPU) controlled real-time systems and more particularly to a scheme for increasing the bandwidth for each CPU of a multi-processor configuration for accessing a commonly shared resource.
Computerized control of telecommunication systems is known in the art. Modern telecommunication systems require vast amounts of processing power in order to provide the varied telecommunication functions commonly in use. Distributed processing or load sharing among CPUs is now common place in large real time systems. The telecommunications industry is no exception to this rule.
In a distributed processing system, CPUs exchange information via a common resource or memory. In this way, the system's tasks may be divided among the available CPUs. Such a system also avoids multiple CPUs initiating the same task by granting access to the common resource or memory to only one CPU at a particular time.
Therefore, when several CPUs attempt to access the common resource or memory, a selection arrangement must allow only one CPU to access the common resource or memory at a time. This hardware is termed contention resolution or arbitration circuitry. One such arbitration controller is shown in U.S. Pat. No. 4,363,096, for an invention entitled Arbitration Controller Providing For Access of A Common Resources By a Duplex Plurality Of Central Processing Units. This patent was issued on Dec. 7, 1982, to the same assignee as that of the present application. U.S. Pat. No. 4,363,096, is hereby incorporated by reference. U.S. Pat. No. 4,376,975, issued on Mar. 15, 1983, also teaches this arbitration scheme. This Patent is entitled Arbitration Controller Providing For Access of A Common Resources by a Plurality of Central Processing Units. This patent is also incorporated by reference.
The above mentioned Patents teach an arbitration circuit which grants access to a common resource to one of a group of CPUs. The number of CPUs in this group may be up to sixteen CPUs. The arbitration scheme employed in these Patents is to circulate granting request to the common resource among the CPUs on a rotational basis (i.e. CPU0 first; CPU1 second; . . . CPU15 then CPU0 again).
The configuration shown in the U.S. Patents mentioned above was designed to handle telecommunication events which typically occur at the rate of 10 milliseconds per event. In situations where there is constant CPU contention for the common resource (i.e. CPUs simultaneously requesting) and when events occur on an average of approximately 10 millisecond intervals, CPU contentions are easily resolved within this time frame, since the available bandwidth is 666 nsec. This arbitration logic was designed in this fashion and worked well to allow multiple processors access to the common resource for telecommunication functions which occurred at approximately 10 millisecond rate.
Public policy requires telecommunication functions including telephone service to operate 24 hours a day continuously without a disruption of service. Therefore, highly reliable telecommunication systems are required. In the above mentioned Patents, each CPU or processor has associated with it local memory. This local memory contains the operating instructions for each CPU. If this local memory becomes mutilated, the processors may not operate efficiently, if at all.
For a telecommunication system outage, no telephone services are provided. Such conditions must be quickly rectified. During outages in the system which employs the above mentioned Patents, reloading the local memory of a CPU from the common memory requires approximately 1 hour. This means that those telecommunication functions and telephone subscribers served by this processor are potentially without service for up to 1 hour.
Improvements were made to the system software which loaded processors whose local memory had become mutilated. This system software is able to reload a processor's local memory very quickly by constantly generating requests for access to the common resource with a frequency of request of approximately 1 request per 666 nanoseconds.
For the duration of the reloading process, each CPU was constantly generating a request for access to the common resource. Due to the rotational scheme employed by the arbitration circuitry of the above mentioned patents, the CPU access bandwidth (frequency of access through the arbitration logic) was found to be insufficient to accommodate the 666 nanosecond bandwidth of multiple constantly requesting CPUs.
A fully equipped group of CPUs along with associated arbitration circuitry includes up to 9 printed wiring cards (PWCs). Since there are two copies of each CPU and arbitration circuit operating in duplex, a fully equipped CPU group may include up to 18 PWCs.
Originally, it was believed that a complete redesign of the arbitration circuitry would be required to accommodate this fast reloading procedure. In addition, it was believed that each of the printed wiring cards would require redesign and relayout. The redesign and relayout functions are extremely costly and require considerable amounts of engineering time and effort.
It, therefore, is an object of the present invention to allow constant access to a common resource by a large number of CPUs, thereby increasing the bandwidth of the CPU/common resource interface, while requiring minimal circuit and engineering changes to the circuitry shown in the above mentioned Patents.